SKILLS

• Engineering – Proven problem solving abilities encompassing areas of Systems, Electrical, and Computer Engineering. Extensive experience in all levels of digital electronics design, including ASIC, FPGA, and board level with ECL, CMOS, and TTL families.

• Project Management – Have managed several graduate students and staff to successful completion of research programs benefiting both industrial and government sponsors. Consistently completed research projects on schedule and within the forecasted budget.

• Simulation and Modeling – Significant experience with VHDL, Markov Models, and Bayesian Belief Networks in modeling complex systems and with several modern programming languages in developing computer aided engineering tools.

• Presentation and Writing – Authored several successful proposals for funding of research in various technical areas. Excellent presentation and writing abilities targeting both technical and non-technical audiences.

• Interpersonal – Proven ability as a bridge builder to enhance overall unity, quality, commitment, and strength of the team.

EXPERIENCE

May 03-Mar 04    Principal Scientist 

UVA Department of Electrical Engineering, Charlottesville, VA

Responsibilities include writing proposals and conducting research in the development and implementation of quantitative safety assessment methodologies for the rail industry. Specific contributions include development of a novel method of estimating Mean-Time-To-Hazardous-Event (MTTHE) using Markov Models and modifying a toolset to support simulation-based fault injection experiments on FPGA designs provided by the client. Additional responsibilities include interacting with sponsors and graduate students, as well as supervising one research staff member.

Aug 94-Aug 01     Research/Senior Scientist

UVA Department of Electrical Engineering, Charlottesville, VA

Promoted from Research Scientist to Senior Scientist in December, 1996. Authored several successful proposals and conducted research in digital and mixed signal designs, including ASIC and FPGA, and system-level design methodologies. Specified hardware and software tools in the support of digital ASIC design in the Center for Semicustom Integrated Systems. These included numerous workstations from Sun Microsystems and Hewlett-Packard, test equipment from HP and others, as well as Computer-Aided-Design software tools from Mentor Graphics Corporation, Vantage Analysis Systems, Synopsys Inc., Cascade Design Automation, and numerous others.

Mar 92-Jul 94     Computer Systems Senior Engineer

UVA Department of Electrical Engineering, Charlottesville, VA

Responsibilities included selecting, installing, and maintaining computing equipment of the department and supervising additional permanent and temporary computer system administration staff. Department’s computing resources included Sun, HP, IBM, and SGI workstations, Macintosh and PC compatibles interconnected via ethernet. Acquired proficiency with SunOS, HPUX, AIX, MS- DOS, MacOS, and Korn shell.

May 88-Mar 92  Graduate Research Assistant

UVA Department of Electrical Engineering, Charlottesville, VA

Devis Developed a modeling methodology to describe computer instruction-set- architectures as part of a broader effort to develop a unified design description and modeling environment for digital systems. Participated in the development of an experimental computer architecture, the WM Machine. Gained extensive experience with VHDL.

Jun 84-Aug 88 Hardware Design Engineer

PERQ Systems Corporation, Pittsburgh, PA

MegaScan Technology, Incorporated, Fairfax, VA

PERQ PERQ was originally Three Rivers Corporation and later spawned MegaScan after restructuring. Responsibilities included specification, design, modeling, PC board design, prototype testing, and diagnostic development for several large digital designs. Solely responsible for these activities in the development of a paged virtual memory management unit, an MC68020-based main processor board for a second-generation workstation, and a TI TMS34010-based video frame buffer for a 300dpi 19-inch monochrome computer monitor. Gained proficiency with C, Pascal, and MC68020 assembly.

EDUCATION

Ph.D. Electrical Engineering, University of Virginia, May, 2003.

DDissertation: Combining Multiple Perspectives in the Specification of a Security Assessment Methodology. Advisor: Ronald D. Williams

M.S. Electrical Engineering, University of Virginia, January, 1990.

Thesis: Implementation-Independent Model of the WM Computer Architecture. Advisor: Barry W. Johnson

B.S. Electrical Engineering, Massachusetts Institute of Technology, June, 1984.

Thesis: High Speed Testing of an LSI Digital Filter.

SELECTED RESEARCH ACTIVITIES

Co-Principal Investigator, "An infogeometric Detector," Harris Technologies Incorporated and Virginia Center for Innovative Technologies, SEAS Proposal No. EE-HTI- 7022-96, 1996-1997

Co-Principal Investigator, "ASIC Chip Set for a 900 MHz and 2.4GHz Transceiver System," Harris Technologies Incorporated, SEAS Proposal No. EE-HTI-7225-97, 1996-1997

Investigator, “RASSP Education and Facilitation,” South Carolina Research Authority, SEAS Proposal No. EE-SCRA-6437-95, 1995 -1997.

Investigator, "Stream Memory Controller," National Science Foundation, 1994-1997

Investigator, "Design and Implementation of an ISOTACH Network," Defense Advanced Research Projects Agency, 1994-1997

SELECTED PUBLICATIONS

Kaufman, L.M., M.H. Salinas, R.D. Williams, R.D., T.C. and Giras, “Integrate Hardware/Software Device Testing for Use in Safety-Critical Systems”, Reliability and Maintainabiliy Symposium, 2003, pp. 132-7

McKee, S.A., W.A. Wulf, J.H. Aylor, R.H. Klenke, M.H. Salinas, S.I. Hong, and D.A.B. Weikle, "Dynamic Access Ordering for Streamed Memory Computations," IEEE Transactions on Computers, vol. 49, no. 11, November, 2000, pp. 1255-71.

McKee, S.A., R.H. Klenke, R.H., K.L. Wright, W.A. Wulf, M.H. Salinas, J.H. Aylor, and A.P. Batson, "Smart Memory Controllers," IEEE Computer, vol. 31, no. 7, July, 1998, pp. 54-63.

T.C Landon, M.H. Salinas, J.H. Aylor, S.A. McKee, and K.L. Wright, "A Systematic Approach to Optimizing and Verifying Synthesized High-Speed ASICs", Proceedings of the IEEE International ASIC '95 Conference, Austin, TX, September, 1995, pp. 245-248.

Salinas, Maximo H., Johnson, Barry W. and Aylor, James H., "Implementation- Independent Model of an Instruction Set Architecture in VHDL", IEEE Design and Test, Volume 10, Number 3, September, 1993, pp. 42-54.

Salinas, Maximo H., "Implementation-Independent Model of an Instruction Set Architecture", Proceedings of the 1991 IEEE International Conference on Computer Design: VLSI in Computers and Processors, IEEE Computer Society Press, October, 1991, pp. 140-145.

PROFESSIONAL ACTIVITIES

Membership Committee Chair and Steering Committee member of 1995 and 1996 International Mentor Graphics Users' Group Conferences (MUG)

Paper reviewer:

     ACM Design Automation Conference

     IEEE Transactions on Computers

MISCELLANEOUS

Tau Beta Pi, Engineering Honor Society

Eta Kappa Nu, Electrical Engineering Honor Society

Institute of Electrical and Elecronics Engineers (IEEE) Senior Member

Association for Computing Machinery (ACM) Member

Extensive international travel.

Fluent in Spanish